Flash memory and other non-volatile memories are structured to have an array of memory cells arranged in rows and columns. Each memory cell comprises a floating gate transistor, and similar to the field-effect transistor, has a control gate, a source region and a drain region. The source region is separated from the drain region by a channel region, but unlike the field-effect transistor, a floating gate typically made of doped polysilicon is disposed over the channel region and electrically isolated from the channel region by a thin insulating layer of gate oxide. The control gate is then formed over the floating gate, and separated by another layer of insulator. Therefore, the floating gate is insulated from the channel, the control gate and all other components of the flash memory cell, thus “floating.”
The flash memory cell can be programmed to store charge representing data, erase the stored charge to prepare for another program operation, or read the data in the programmed memory cell. The flash memory cell is programmed by storing charge on the floating gate, which thereafter remains on the gate for an indefinite period. Charge is stored on the floating gate by applying appropriate voltages to the control gate and the drain region or the source region. An electrical charge may be stored in the floating gate by a number of different ways. For example, programming can be performed by channel hot-electron injection (CHE), where a sufficiently large positive bias is applied to the control gate while the source is grounded to attract electrons through the gate oxide and into the floating gate region. The voltage applied to the control gate, called the programming voltage, determines the amount of charge to store on the floating gate. Before programming, the flash memory cell is generally erased by removing any charge trapped in the floating gate. An erase voltage is applied to the control gate to generate a gate voltage having a polarity opposite to that used in the programming operation. For example, in a process called drain-Fowler-Nordheim (FN) tunneling, a relatively large negative bias is applied on the control gate and a positive bias is applied to the drain region to cause the electrons to tunnel towards the drain through the gate oxide and deplete any charge from the floating gate.
After a memory cell has been programmed, the flash memory cell may be read by applying a positive control gate to source voltage, called read voltage. The amount of charge stored on the flash memory cell determines the magnitude of the threshold voltage that must be applied to the control gate to allow the flash memory cell to conduct current between the source and the drain. The source is coupled to ground, and a suitable positive voltage is applied to the drain, which is used as the output terminal of the cell. As negative charge is added to the floating gate, the threshold voltage of the flash memory cell increases. During a read operation, the read voltage applied to the control gate must be large enough to render the cell conductive if no charge is stored on the floating gate, but not large enough to render the cell conductive if charge is stored on the floating gate. Therefore, if the floating gate of the flash memory cell is charged, the drain will remain at the positive voltage and output a “1” value. If the floating gate of the flash memory cell is not charged, the cell will ground the drain and output a “0” value.
Two types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic flash memory cell configuration for each is arranged. FIG. 1 illustrates a typical NOR flash memory array 10 of conventional design. The array 10 includes memory cells 18 arranged in rows and columns. The drains of the memory cells 18 of a single column are coupled to each other in series by a common bitline 20 (BL-1 to BL-3), and the gates of the memory cells 18 of a single row are coupled to each other by a common select line 30 (WL-1 to WL-3). The sources of the memory cells 18 in the array are additionally coupled to an array source 40.
The read operation is performed on a row-by-row basis, where the read voltage is applied to a selected select line 30, thereby applying the read voltage to the control gates of all the memory cells in that row. The array source 40 is coupled to ground and the bitline 20 for each column is precharged to a supply voltage VCC, such that if the gate to source voltage of each memory cell 18 of the selected row is greater than the threshold voltage, the channel region of the memory cell 18 will become conductive. However, since charge must be transported through the gate oxide during programming and erase operations, memory cell 18 will get some incremental damage over time, eventually making it difficult to properly distinguish between a “1” and a “0”. This limits the number of program/erase cycles to typically 1 million.
FIG. 2 is a block diagram illustrating the formation of a prior art metal oxide semiconductor flash memory cell 200 having a floating gate 212. The flash memory cell 200 includes a control gate 230 formed over the floating gate 212. Both the control gate 230 and the floating gate 212 are deposited using a standard polysilicon layer, except the floating gate 212 is encapsulated by a dielectric material (not shown). The control gate 230 is connected to the select line 30 of FIG. 1, and is separated from the floating gate 212 by an insulator 232 of appropriate material and thickeness. A thin layer of gate oxide 233 separates the floating gate 212 from the silicon surface of a channel region 225, which is formed by doping commercially available silicon material. The channel region 225 separates a source region 214 and a drain region 216, which are also formed by appropriately doping the silicon layer, and may be either p-type or n-type depending on the transistor-type of the memory cell 200. The source and drain regions 214, 216 are isolated from the source and drain regions of adjacent memory cells by shallow trenches 220, that are formed by depositing one of several types of dielectric material known in the art.
As the control gate 230 is subjected to high voltage levels during every program and erase operation (either by CHE or FN tunneling), the silicon surface of the memory cell 200 body and the gate oxide layers 233 between the gates 212, 230 are incrementally damaged due to hot electrons that are induced by the higher voltage levels. Charges may be trapped at the silicon-oxide interface and within the gate oxide layers 233. As the electrons become heated by the high energy fields, their kinetic energy increases, causing the electrons to bombard the silicon-oxide interface, and become trapped. Consequently, the damage to the oxide layers 233 and silicon surface gradually changes the properties of the memory cell 200 so much that the memory cell's 200 threshold voltage may be modified. The damaged interface and the oxide layers 233 may also cause charge to leak from the control gate 230, the floating gate 212 or the channel region 225 due to one or more of the oxide layers 233 deteriorating due to trapped electrons. The read voltage level applied to the control gate 230 may become insufficient to carry out a proper read operation as the properties of the memory cell 200 are altered. Eventually, it becomes difficult to distinguish the different threshold voltage levels of the memory cell 200 during a read operation. Additionally, the type of gate oxide and the thickness of the gate oxide layer are limited to certain materials, known in the art, that must achieve the particularized threshold voltage while withstanding the damage to the control gate 230 in order to meet industry standard program/erase cycles during the life of the cell.
There is, therefore, a need to, for example, avoid damaging effects of the higher voltage levels on the control gate.